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-- Company: 
-- Engineer: 
-- 
-- Create Date:    16:50:47 11/28/2010 
-- Design Name: 
-- Module Name:    sp_reg - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.constants.all;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity sp_reg is
	port (
		clk			: in	std_logic;
		reset			: in	std_logic;
		we				: in	std_logic;
		serial_in		: in	std_logic;
		parallel_out	: out	std_logic_vector(DATA_SIZE-1 downto 0)
	);
end sp_reg;

architecture Behavioral of sp_reg is
begin
	-- purpose : shift in the register 1 bit at each clock cycle when write enable signal is active.
	-- type    : sequential
	P_SP_REGISTER : process(clk, reset, we, serial_in)
		variable tmp_out : std_logic_vector(DATA_SIZE-1 downto 0) := (others => '0');
	begin
		if ( reset = '1' ) then
			tmp_out := (others => '0');
		elsif ( clk'event and clk = '0' ) then
			if ( we = '1' ) then
				tmp_out := tmp_out(DATA_SIZE-2 downto 0) & serial_in;
			end if;
		end if;
		parallel_out <= tmp_out;
	end process;
	
end Behavioral;

